 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register April 1988 Revised October 2000 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description The 74F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer words. By means of a separate clock, the contents of the shift register are transferred to the storage register. The contents of the storage register can also be loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel loading. Features s Serial-to-parallel converter s 16-Bit serial I/O shift register s 16-Bit parallel out storage register s Recirculating parallel transfer s Expandable for longer words s Slim 24 lead package s 74F675A version prevents false clocking through CS or R/W inputs Ordering Code: Order Number 74F675ASC 74F675APC 74F675ASPC Package Number M24B N24A N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbols IEEE/IEC Connection Diagram (c) 2000 Fairchild Semiconductor Corporation DS009587 www.fairchildsemi.com 74F675A Unit Loading/Fan Out Pin Names SI CS SHCP STCP R/W SO Q0-Q15 Serial Data Input Chip Select Input (Active LOW) Shift Clock Pulse Input (Active Falling Edge) Store Clock Pulse Input (Active Rising Edge) Read/Write Input Serial Data Output Parallel Data Outputs Description U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA -1 mA/20 mA -1 mA/20 mA Functional Description The 16-Bit shift register operates in one of four modes, as determined by the signals applied to the Chip Select (CS), Read/Write (R/W) and Store Clock Pulse (STCP) input. State changes are indicated by the falling edge of the Shift Clock Pulse (SHCP). In the Shift Right mode, data enters D0 from the Serial Input (SI) pin and exits from Q15 via the Serial Data Output (SO) pin. In the Parallel Load mode, data from the storage register outputs enter the shift register and serial shifting is inhibited. The storage register is in the Hold mode when either CS or R/W is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register on the rising edge of STCP. To prevent false clocking of the shift register, SHCP should be in the LOW state during a LOW-to-HIGH transition of CS. To prevent false clocking of the storage register, STCP should be LOW during a HIGH-to-LOW transition of CS if R/W is LOW, and should also be LOW during a HIGH-to-LOW transition of R/W if CS is LOW. Shift Register Operations Table Control Inputs CS H L L L R/W X L H H SHCP STCP Operating Mode Hold Shift Right Shift Right Parallel Load, No Shifting Storage Register Operations Table Inputs CS H L L R/W X H L STCP X Operating Mode Hold Hold Parallel Load X X X L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = HIGH-to-LOW Transition = LOW-to-HIGH Transition X Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F675A Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V -0.5V to VCC -0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICCH ICCL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current Power Supply Current -60 106 106 4.75 3.75 -0.6 -150 160 160 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A A V A mA mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 0V VO = HIGH VO = LOW 3 www.fairchildsemi.com 74F675A AC Electrical Characteristics TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay STCP to Qn Propagation Delay SHCP to SO 100 3.0 3.0 4.0 4.5 VCC = +5.0V CL = 50 pF Typ 130 8.0 10.5 7.0 8.0 10.5 13.5 9.5 10.5 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 85 2.5 2.5 3.5 4.0 12.0 15.0 10.5 12.0 Max MHz ns ns Units AC Operating Requirements TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(H) tW(L) tS(L) tH(H) Setup Time, HIGH or LOW CS or R/W to STCP Hold Time, HIGH or LOW CS or R/W to STCP Setup Time, HIGH or LOW SI to SHCP Hold Time, HIGH or LOW SI to SHCP Setup Time, HIGH or LOW R/W to SHCP Hold Time, HIGH or LOW R/W to SHCP Setup Time, HIGH or LOW STCP to SHCP Hold Time, HIGH or LOW STCP to SHCP Setup Time, HIGH or LOW CS to SHCP Hold Time, HIGH or LOW CS to SHCP SHCP Pulse Width HIGH or LOW STCP Pulse Width HIGH or LOW SHCP to STCP SHCP to STCP 3.5 5.5 0 0 3.0 3.0 3.0 3.0 6.5 9.0 0 0 7.0 7.0 0 0 3.0 3.0 3.0 3.0 5.0 5.0 6.0 5.0 8.0 0.0 Max TA = 0C to +70C VCC = +5.0V Min 4.0 6.5 0 0 3.5 3.5 3.5 3.5 7.5 10.0 0 0 8.0 8.0 0 0 3.5 3.5 3.5 3.5 6.0 6.0 7.0 6.0 9.0 0.0 ns ns ns ns ns ns ns ns Max Units www.fairchildsemi.com 4 74F675A Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide Package Number N24A 5 www.fairchildsemi.com 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
Price & Availability of 74F675A00
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |